Minicomputers typically include a central processing unit which performs computations on data stored in a random access memory in conformance with instructions also stored in the random access memory (RAM). The data and instructions are the software which the user stores ("programs") in the RAM and may be easily changed by the user. The computations performed by the central processing unit in response to the instructions stored by the user in the RAM are controlled by microprograms permanently stored within the central processing unit itself in one of more non-volatile read only memories (ROM).
The versatility of minicomputers has significantly increased recently due in large part to the role played by the ROM. The mode of operation of the central processing unit may be customized for specific applications by programming the contents of the ROM so that the microprograms contained therein and executed by the central processing unit in response to user software are adapted to perform most efficiently for a specific task. In the prior art, a ROM could only be erased by the use of ultraviolet light, a procedure consuming as much as half an hour. Therefore, the user or purchaser of a minicomputer had to rely on the manufacturer to erase and reprogram the ROMs.
A very recent development has been the electrically erasable programmable read only memory (EEPROM) which does not require the use of ultraviolet or other radiation for complete erasure. Whereas in the prior art the minicomputer hardware had to be physically altered by factory technicians in order to reprogram the ROM, an EEPROM requires no such physical alteration inasmuch as erasure is controlled electrically and may therefore be performed by the user simply by entering the correct command into the cental processing unit.
Each cell of the EEPROM is a floating gate tunneling metal oxide semiconductor field effect transistor (FATMOS), a particular type of which is described by U.S. Pat. No. 4,115,914 to Eliyahou Harari entitled "Electrically Erasable Non-Volatile Semiconductor Memory" and assigned to the assignee of the present application. The floating gate of the FATMOS may be electrically charged or discharged to regulate current flow between its source and drain, corresponding to a permanently stored logic "1" or logic "0", respectively.
Currently available EEPROMs capable of storing 8,000 binary bits, for example, include 8,192 FATMOS transistors arranged in a planar matrix of rows and columns, each row of FATMOS transistors having a common control gate and each column of FATMOS transistors sharing commonly connected source and drain diffusions. Thus, each memory cell comprising a single FATMOS transistor is individually addressable by applying electrical signals to a certain row and a certain column of the memory. For example, in order to write a logic "1" or "0" into a particular cell of the memory, a voltage is applied to the control gate corresponding to the row of the selected memory cell while a voltage corresponding to either a logic "1" or "0" is applied to the source or drain corresponding to the column of the selected cell. A significant problem with this arrangement is that it is necessary to provide an additional metal oxide semiconductor field effect transistor (MOSFET) to act as an "AND" gate in each memory cell in order to enable the user to select a single row of memory cells while writing data into the memory without accidently writing or erasing memory cells in other rows.
The current developmental thrust of minicomputer technology is toward dramatic density improvement. Unfortunately, the presence of the additional MOSFET transistor in each memory cell of the EEPROM nearly doubles the size of each memory cell, prompting those skilled in the art to seek solutions which would eliminate the extra MOSFET transistor from each EEPROM memory cell while providing the capability to write a binary bit into a selected memory cell which is addressed according to its row and column without accidentally writing or erasing other cells. One solution discovered in the prior art, commonly called the "half-select" system, is to use three different voltage levels which may be applied to the gate and drain of rows and columns, respectively, of memory cells, each memory cell comprising a single FATMOS transistor only. The potential difference between the highest and lowest voltage level in this system is sufficient, when applied between the substrate and the overlying control gate, to charge or discharge the FATMOS floating gate in order to write or erase data, while the third voltage level is intermediate between these two levels. When a single memory cell is selected for writing, some memory cells have no potential difference between their control gate and drain ("no select"), others have only half the requisite voltage difference between their control gate and drain ("drain select") by reason of the application of the intermediate voltage level to these cells, and only the selected memory cell has the full voltage difference between its control gate and drain. A significant disadvantage of the half-select system is that the memory cells which are half selected are subject to some accidental charging or discharging of their floating gates. Therefore, although the half-select system does eliminate the extra MOSFET transistor from each memory, the system is unreliable in that many memory cells may experience accidental writing, generating bit errors in the memory.
It has therefore been a goal in the art to provide an EEPROM which does not require an additional MOSFET transistor in each memory cell and which does not require the use of a half-select system, and yet provides a reliable selection of a single memory cell for writing data while precluding accidental simultaneous erasure or writing in non-selected cells.